The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Dec. 21, 2018
Applicant:

Gyrfalcon Technology Inc., Milpitas, CA (US);

Inventors:

Chyu-Jiuh Torng, Dublin, CA (US);

Daniel H. Liu, San Jose, CA (US);

Wenhan Zhang, Mississauga, CA;

Hualiang Yu, San Jose, CA (US);

Assignee:

Gyrfalcon Technology Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/07 (2006.01); G11C 29/18 (2006.01); G11C 29/44 (2006.01); G06N 3/063 (2006.01);
U.S. Cl.
CPC ...
G06F 11/076 (2013.01); G06N 3/063 (2013.01); G11C 29/18 (2013.01); G11C 29/44 (2013.01); G11C 2029/1806 (2013.01);
Abstract

This disclosure relates to testing of integrated artificial intelligence (AI) circuit with embedded memory to improve effective chip yield and to mapping addressable memory segments of the embedded memory to multilayer AI networks at the network level, layer level, parameter level, and bit level based on bit error rate (BER) of the addressable memory segments. The disclosed methods and systems allows for deployment of one or more multilayer AI networks in an AI circuit with sufficient model accuracy even when the embedded memory has an overall BER higher than a preferred overall threshold.


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