The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Oct. 07, 2018
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Christopher J. Corsi, Durham, NC (US);

Sudhanshu Goswami, Durham, NC (US);

Kevin Kauffman, Durham, NC (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 12/02 (2006.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/5077 (2013.01); G06F 9/3004 (2013.01); G06F 9/5016 (2013.01); G06F 12/0246 (2013.01); G06F 2209/5021 (2013.01); G06F 2209/5022 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/2542 (2013.01);
Abstract

This disclosure is directed to a technique for memory management where physical memory areas may be partitions into a hierarchy of portions, the hierarchy may include a domain level that includes a page level that includes a slice level that includes an object level. Objects within a slice are a consistent size but may be different sized for different slices. A set of states reflecting memory usage status for each of the slices includes: a clean state for unused; a partial state; a full state; and a dirty state. Responses to allocation requests may be performed by selecting objects that are in a most preferred state based on a state allocation cost and a memory allocation cost either alone or in combination. A compact memory layout may be used to reduce run-time fragmentation of memory.


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