Self-timed clocked processor architecture

Abstract

There is disclosed a self-timed clocked synchronous processor having at least one combinatorial logic (CL) block for processing data. The CL block has a critical path with a propagation delay that is a minimum allowable clock period to perform data processing of the CL block at an operating voltage of the processor without a timing error due to a register of the processor receiving the critical path output before it is completed. The processor has a critical path oscillator to simulate the critical path propagation delay and create an oscillator clock signal with a period greater than the minimum allowable clock period. The oscillator clock signal is used to clock the register, avoiding the timing error. A power manager outputs an operating voltage to the processor that causes the oscillator clock to be faster than an external time reference period for completing the current task of the processor.