The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Nov. 15, 2017
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Jose de Jesus Pineda de Gyvez, Eindhoven, NL;

Hamed Fatemi, Eindhoven, NL;

Manuele Rusci, Siena, IT;

Luca Benini, Ferrara, IT;

Elisabetta Farella, Bologna, IT;

Davide Rossi, Bologna, IT;

Assignee:

NXP B.V., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 1/324 (2019.01); G06F 11/34 (2006.01); G06F 9/48 (2006.01); G06F 1/3228 (2019.01); G06F 1/329 (2019.01); G06F 1/3234 (2019.01);
U.S. Cl.
CPC ...
G06F 1/324 (2013.01); G06F 1/329 (2013.01); G06F 1/3228 (2013.01); G06F 1/3243 (2013.01); G06F 9/485 (2013.01); G06F 11/3414 (2013.01);
Abstract

A technique for managing power in an embedded processing system includes generating a workload model for the embedded processing system in response to a control signal, an event status signal, and a reference clock signal. The control signal is received from a peripheral device. The event status signal is received from an event processor configured to control execution of tasks by a processor core of the embedded processing system. The technique includes providing power configuration information to the processor core. The power configuration information corresponds to an operating point selected based on the control signal, the event status signal, the reference clock signal, the workload model, and a predetermined energy model.


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