The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

May. 02, 2019
Applicant:

Olympus Corporation, Tokyo, JP;

Inventors:

Koji Kojima, Hachioji, JP;

Hideyuki Kugimiya, Hachioji, JP;

Ryo Koshida, Fuchu, JP;

Assignee:

OLYMPUS CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 13/00 (2018.01); H04N 7/18 (2006.01); A61B 1/04 (2006.01); A61B 1/00 (2006.01); H04N 13/204 (2018.01); A61B 1/045 (2006.01); A61B 1/06 (2006.01); G02B 23/24 (2006.01); H04N 5/225 (2006.01);
U.S. Cl.
CPC ...
A61B 1/00009 (2013.01); A61B 1/00 (2013.01); A61B 1/04 (2013.01); A61B 1/045 (2013.01); A61B 1/0676 (2013.01); G02B 23/24 (2013.01); G02B 23/2415 (2013.01); H04N 7/18 (2013.01); H04N 13/204 (2018.05); A61B 1/0002 (2013.01); A61B 1/00045 (2013.01); G02B 23/2484 (2013.01); G06T 2207/10068 (2013.01); H04N 2005/2255 (2013.01);
Abstract

An endoscope system includes: a first processor configured to perform first image processing on a set of image data; a second processor configured to perform second image processing on another set of image data; a third processor configured to generate, based on sets of image data output from the first and second processors, display image data; a recorder configured to record therein image data based on the sets of image data output from the first and second processors; a fourth processor configured to generate a first synchronization signal for synchronization among the first processor, the second processor, and the third processor; a fifth processor configured to generate a second synchronization signal for synchronization between the third processor and the recorder; and a controller configured to select one of the first and second synchronization signals, and perform control for synchronization between the third processor and the recorder.


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