The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2020

Filed:

Apr. 24, 2014
Applicant:

Fuji Corporation, Chiryu, JP;

Inventor:

Yoshihiro Yasui, Nagoya, JP;

Assignee:

FUJI CORPORATION, Chiryu, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 13/04 (2006.01); H05K 13/08 (2006.01);
U.S. Cl.
CPC ...
H05K 13/04 (2013.01); H05K 13/0452 (2013.01); H05K 13/0495 (2013.01); H05K 13/08 (2013.01); H05K 13/085 (2018.08); Y10T 29/53174 (2015.01); Y10T 29/53187 (2015.01);
Abstract

With multiple-board substrate defined as a circuit substrate provided with multiple boards of circuit pattern on which multiple electronic components are mounted, when performing mounting work of multiple electronic components on a multiple-board substrate using three mounters lined up in a row, electronic component mounting work procedures are set such that mounting work of electronic components for each of multiple circuit patterns is performed by all three mounters. Work procedures for mounting work of electronic components surrounded by the dashed lines are set to a first mounter, work procedures for mounting work of electronic components surrounded by the single-dashed solid lines are set to a second mounter, and work procedures for mounting work of electronic components surrounded by the double-dashed solid lines are set to a third mounter.


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