Bias minimization for successive image reconstruction based on embedded codec circuitry

Abstract

An embedded decoder circuitry for bias minimization in successively reconstructed images from a decoded image obtained from an encoded input image, includes an on-chip memory and a bias control circuit communicatively coupled to the on-chip memory. The on-chip memory stores transform-domain compressed data that includes a plurality of transform blocks of an input image. The bias control circuit is configured to determine a set of conditions associated with each transform coefficient in a transform block of the encoded input image and modify a set of transform coefficients from the plurality of transform coefficients in the transform block based on determination of the set of conditions. The bias control circuit is further configured to generate a decoded image that exhibits a reduced error propagation in successively reconstructed images with respect to the input image, based on inverse transformation of each transform block of the encoded input image.