The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2020

Filed:

Aug. 01, 2018
Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventors:

Santosh Manjunath Bhandarkar, Chandler, AZ (US);

Alex Dumais, Gilbert, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/158 (2006.01); H02M 1/42 (2007.01); H03K 17/13 (2006.01);
U.S. Cl.
CPC ...
H02M 1/4225 (2013.01); H02M 3/1584 (2013.01); H03K 17/133 (2013.01); H02M 2003/1586 (2013.01);
Abstract

A circuit arrangement, signal processor, and method for interleaved switched boundary mode power conversion are disclosed. The circuit arrangement comprises at least an input for receiving an alternating input voltage from a power supply; an output to provide an output voltage to a load; a first interleaved circuit comprising: a first energy storage device; and a first controllable switching device; and one or more secondary interleaved circuits, each comprising: a secondary energy storage device; and a secondary controllable switching device; and a signal processor. The signal processor is connected to the controllable switching devices and comprises at least a first switching cycle controller, configured for cycled zero-current switching operation of the first controllable switching device; and one or more secondary switching cycle controllers, configured for cycled zero-current switching operation of the one or more secondary controllable switching devices The signal processor is configured to disable one or more of the interleaved circuits when the alternating input voltage is lower than a first threshold voltage to reduce the zero-crossing time.


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