The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2020

Filed:

Dec. 05, 2018
Applicant:

SK Hynix Inc., Icheon-si Gyeonggi-do, KR;

Inventors:

Hyuck Sang Yim, Seoul, KR;

Myung Sun Song, Incheon, KR;

Assignee:

SK hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 27/24 (2006.01); G11C 7/18 (2006.01); G11C 8/14 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 45/06 (2013.01); G11C 7/18 (2013.01); G11C 8/14 (2013.01); G11C 13/0004 (2013.01); H01L 27/2463 (2013.01); H01L 45/1253 (2013.01); H01L 45/144 (2013.01); H01L 45/1666 (2013.01);
Abstract

A resistive memory device may include a plurality of MATs, row control blocks, a plurality of word lines, a plurality of bit lines and memory cells. Each of the row control blocks may be interposed between the MATs. Each of the row control blocks may include a control element. The word lines may be arranged spaced apart from each other by a substantially uniform gap on the MATs. The bit lines may overlap with the word lines. The memory cells may be located between the word lines and the bit lines. Each of the word lines may be electrically connected with the control element of each of the row control blocks via a connection path.


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