The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2020

Filed:

Sep. 04, 2019
Applicant:

Kaneka Corporation, Osaka, JP;

Inventors:

Katsunori Konishi, Osaka, JP;

Kunta Yoshikawa, Osaka, JP;

Hayato Kawasaki, Osaka, JP;

Kunihiro Nakano, Osaka, JP;

Assignee:

KANEKA CORPORATION, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/18 (2006.01); H01L 31/072 (2012.01); H01L 31/0224 (2006.01); H01L 31/0747 (2012.01);
U.S. Cl.
CPC ...
H01L 31/022441 (2013.01); H01L 31/072 (2013.01); H01L 31/0747 (2013.01); H01L 31/18 (2013.01); H01L 31/1804 (2013.01); Y02E 10/50 (2013.01); Y02P 70/521 (2015.11);
Abstract

A method for manufacturing a photoelectric conversion device, wherein the photoelectric conversion device includes a semiconductor substrate having a first conductivity-type region, a second conductivity-type region, and a boundary region on a first principal surface of a semiconductor substrate, the boundary region being in contact with and separating the first conductivity-type region and the second conductivity-type region, the method including: stacking a second conductivity-type semiconductor layer over the second conductivity-type region and the boundary region on the first principal surface of the semiconductor substrate; stacking an insulating layer over the second conductivity-type semiconductor layer in the boundary region; stacking a first conductivity-type semiconductor layer over the first conductivity-type region on the first principal surface of the semiconductor substrate and on the insulating layer; stacking an electrode layer on the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer; and forming a separation groove that separates the electrode layer.


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