The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2020

Filed:

Apr. 03, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Sung Il Park, Suwon-si, KR;

Jung Gun You, Ansan-si, KR;

Dong Hun Lee, Seoul, KR;

Yun Il Lee, Anyang-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78642 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/42392 (2013.01); H01L 29/4908 (2013.01); H01L 29/66553 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H01L 29/42376 (2013.01); H01L 2029/42388 (2013.01);
Abstract

A semiconductor device includes a substrate; a vertical channel structure including a pair of active fins extended in a first direction, perpendicular to an upper surface of the substrate, and an insulating portion interposed between the pair of active fins; an upper source/drain disposed on the vertical channel structure; a lower source/drain disposed below the vertical channel structure and on the substrate; a gate electrode disposed between the upper source/drain and the lower source/drain and surrounding the vertical channel structure; and a gate dielectric layer disposed between the gate electrode and the vertical channel structure. An interval between the gate electrode and the upper source/drain may be smaller than an interval between the gate electrode and the lower source/drain in the first direction.


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