The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2020

Filed:

Jul. 30, 2018
Applicant:

Nscore, Inc., Fukuoka, JP;

Inventor:

Tadahiko Horiuchi, Kanagawa, JP;

Assignee:

NSCore, INC., Fukuoka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 29/08 (2006.01); H01L 27/02 (2006.01); H01L 29/78 (2006.01); H04L 9/32 (2006.01); G11C 11/418 (2006.01); G11C 11/412 (2006.01); H01L 29/47 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); G11C 11/412 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); H01L 27/0207 (2013.01); H01L 29/0847 (2013.01); H01L 29/47 (2013.01); H01L 29/7835 (2013.01); H01L 29/7839 (2013.01); H04L 9/3278 (2013.01);
Abstract

It is provided a circuit for generating finger print code data comprising: plural pairs of first transistors, each of the first transistors having a source formed in the substrate, a drain formed in the substrate, a channel formed in the substrate between the source and the drain, a gate insulating layer formed on the channel, a gate electrode formed over the gate insulating layer, and an insulating sidewall formed at a side surface of the gate electrode; plural pairs of cross coupled second transistors, each of the plural pairs of cross coupled second transistors having drains and commonly connected sources, corresponding to each of the plural pairs of first transistors; and plural pairs of third transistors, each of the plural pairs of third transistors corresponding to each of the plural pairs of cross coupled second transistors.


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