The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2020

Filed:

Jun. 23, 2017
Applicant:

Mitsubishi Gas Chemical Company, Inc., Tokyo, JP;

Inventors:

Syunsuke Hirano, Yamagata, JP;

Yoshihiro Kato, Yamagata, JP;

Takaaki Ogashiwa, Yamagata, JP;

Kazuaki Kawashita, Yamagata, JP;

Youichi Nakajima, Yamagata, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); B32B 15/08 (2006.01); H05K 3/46 (2006.01); H01L 23/498 (2006.01); B32B 15/20 (2006.01); C23C 18/38 (2006.01); C23F 17/00 (2006.01); C25D 7/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4857 (2013.01); B32B 15/08 (2013.01); B32B 15/20 (2013.01); H01L 23/49822 (2013.01); H05K 3/46 (2013.01); B32B 2457/08 (2013.01); C23C 18/38 (2013.01); C23F 17/00 (2013.01); C25D 7/00 (2013.01);
Abstract

A method for manufacturing a package substrate for mounting a semiconductor device, including a substrate forming step (a) of forming a supporting substrate for circuit formation including a first insulating resin layer, a release layer including at least a silicon compound, and ultrathin copper foil having a thickness of 1 μm to 5 μm, in this order; a first wiring conductor forming step (b) of forming a first wiring conductor on the ultrathin copper foil of the supporting substrate for circuit formation by pattern copper electroplating; a lamination step (c) of disposing a second insulating resin layer so as to be in contact with the first wiring conductor, and heating and pressurizing the second insulating resin layer for lamination; a second wiring conductor forming step (d) of forming in the second insulating resin layer a non-through hole reaching the first wiring conductor and connecting an inner wall of the non-through hole.


Find Patent Forward Citations

Loading…