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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10726921 B1

PDFFull Text
Expired
Date of Patent:
Jul. 28, 2020

Filed:

Mar. 30, 2018

Increased terrace configuration for non-volatile memory

Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Chia-Lin Hsiung, Campbell, CA (US);

Fumiaki Toyama, Cupertino, CA (US);

Tai-Yuan Tseng, Milpitas, CA (US);

Yan Li, Milpitas, CA (US);

Assignee:

SanDisk Technologies LLC, Addison, TX (US);

Attorney:

Vierra Magen Marcus LLP

Primary Examiner:

Viet Q Nguyen

Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/08 (2006.01); H01L 27/11556 (2017.01); H01L 23/528 (2006.01); G11C 16/04 (2006.01); H01L 27/11582 (2017.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 16/08 (2013.01); G11C 11/5621 (2013.01); G11C 11/5671 (2013.01); G11C 16/0458 (2013.01); G11C 16/0483 (2013.01); H01L 23/528 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); G11C 16/0408 (2013.01); G11C 16/0466 (2013.01);
Abstract

A three-dimensional block includes a stack comprising a plurality of control gate layers configured to bias memory cells of the block. The block includes a plurality of track regions that includes three or more hookup regions. The plurality of track regions separate the memory cells into three memory cell regions. Tracks extending in the track regions supply voltages to the hookup regions. A system includes a memory plane of blocks, and a plurality of track regions, each extending across the memory plane of blocks.

Find Patent Forward Citations

Hsiung, Chia-Lin. (2020). Increased terrace configuration for non-volatile memory (U.S. Patent No. 10726921). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10726921

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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