The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2020

Filed:

Jun. 01, 2017
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Beijing Boe Optoelectronics Technology Co., Ltd., Beijing, CN;

Inventors:

Zijin Lin, Beijing, CN;

Haisheng Zhao, Beijing, CN;

Xiaoguang Pei, Beijing, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/00 (2006.01); G02F 1/13 (2006.01); G02F 1/1362 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
G09G 3/006 (2013.01); G02F 1/1309 (2013.01); G02F 1/136204 (2013.01); H01L 27/1214 (2013.01);
Abstract

An array substrate is disclosed, which includes a substrate, at least one test line, an insulating layer, and an electrostatic shielding pattern. The at least one test line is disposed over the substrate. The insulating layer is disposed over the at least one test line. The electrostatic shielding pattern is disposed over, and insulated by the insulating layer from, the at least one test line in the array substrate. The electrostatic shielding pattern is configured to absorb, and guide out from the array substrate, static electricity to thereby avoid the static electricity from entering an interior of the array substrate via the at least one test line. A method for manufacturing the array substrate, and a display panel containing the array substrate are also provided in the disclosure.


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