The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10726185 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 28, 2020

Filed:

Oct. 11, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Jayaprakash Udhayakumar, Bangalore, IN;

Sumantra Sarkar, Hebbal, IN;

Chaitanya Kompalli, Bangalore, IN;

Srinivasa Rahul Batchu, Bangalore, IN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 111/04 (2020.01); G06F 111/20 (2020.01); G06F 119/12 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 2111/04 (2020.01); G06F 2111/20 (2020.01); G06F 2119/12 (2020.01); G06F 2119/18 (2020.01);
Abstract

Aspects include performing integrated circuit design. A processor identifies a child block of an integrated circuit for placement of a buffer-bay to insert a buffer in a portion of the integrated circuit reserved for the child block. The buffer-bay is divided into a plurality of buffer-bay segments. Parent-level routing information and one or more boundary conditions are analyzed to determine a plurality of placement options for the buffer-bay segments. A best possible placement is selected from the plurality of placement options for the buffer-bay segments as a planned buffer-bay layout. A routing of the integrated circuit is performed based on the planned buffer-bay layout.


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