The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2020

Filed:

Jan. 16, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Tatsunori Kanai, Yokohama Kanagawa, JP;

Tetsuro Kimura, Tama Tokyo, JP;

Yusuke Shirota, Yokohama Kanagawa, JP;

Masaya Tarui, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/20 (2006.01); G06F 15/78 (2006.01); G06F 1/30 (2006.01); G11C 16/30 (2006.01); G11C 7/04 (2006.01); G11C 11/00 (2006.01); G06F 1/26 (2006.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01); G11C 14/00 (2006.01); H05K 1/18 (2006.01); G11C 16/22 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2015 (2013.01); G06F 1/263 (2013.01); G06F 1/30 (2013.01); G06F 11/20 (2013.01); G06F 11/2025 (2013.01); G06F 15/78 (2013.01); G11C 7/04 (2013.01); G11C 11/005 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/1697 (2013.01); G11C 13/004 (2013.01); G11C 13/0038 (2013.01); G11C 13/0069 (2013.01); G11C 14/009 (2013.01); G11C 14/0036 (2013.01); G11C 14/0045 (2013.01); G11C 14/0081 (2013.01); G11C 16/30 (2013.01); H05K 1/181 (2013.01); G06F 2201/85 (2013.01); G11C 16/225 (2013.01); H05K 2201/10053 (2013.01); H05K 2201/10159 (2013.01);
Abstract

According to an embodiment, an electronic circuit board includes a nonvolatile memory, a reading circuit to read data stored in the nonvolatile memory, a switch, and a communication circuit. When power is supplied from a first power source, the switch performs switching to a first state in which the nonvolatile memory and a host device configured to read and write data from and in the nonvolatile memory are connected. When power is supplied from a second power source, the switch performs switching to a second state in which the host device and the nonvolatile memory are not connected and the reading circuit and the nonvolatile memory are connected. The communication circuit transmits, to an external device, the data read by the reading circuit from the nonvolatile memory when power is being supplied from the second power source.


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