The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2020

Filed:

Oct. 13, 2016
Applicant:

Red Hat Israel, Ltd., Raanana, IL;

Inventors:

Michael Tsirkin, Yokneam Yillit, IL;

Paolo Bonzini, Turate, IT;

Assignee:

Red Hat Israel, Ltd., Raanana, IL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 12/1009 (2016.01); G06F 12/1045 (2016.01); G06F 12/1081 (2016.01); G06F 12/1027 (2016.01);
U.S. Cl.
CPC ...
G06F 9/45558 (2013.01); G06F 12/1009 (2013.01); G06F 12/1027 (2013.01); G06F 12/1063 (2013.01); G06F 12/1081 (2013.01); G06F 2009/45579 (2013.01); G06F 2009/45583 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/152 (2013.01); G06F 2212/68 (2013.01);
Abstract

A hypervisor configures a page table entry in a host page table to map an address associated with memory-mapped input-output (MMIO) for a virtual device of a guest of the hypervisor to an input/output (I/O) instruction. The address is marked in the page table entry as a hypervisor exit entry, and the page table entry to cause an exit to the hypervisor responsive to the guest attempting to access the address. Responsive to detecting an exit to the hypervisor caused by the guest attempting to access the address, the hypervisor receives the I/O instruction mapped to the address that caused the exit. The hypervisor then executes the I/O instruction on behalf of the guest.


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