The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2020

Filed:

Sep. 11, 2017
Applicant:

Nec Corporation, Tokyo, JP;

Inventors:

Xu Bai, Tokyo, JP;

Toshitsugu Sakamoto, Tokyo, JP;

Yukihide Tsuji, Tokyo, JP;

Ayuka Tada, Tokyo, JP;

Makoto Miyamura, Tokyo, JP;

Ryusuke Nebashi, Tokyo, JP;

Assignee:

NEC CORPORATION, Minato-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/17756 (2020.01); H03K 19/177 (2020.01); H03K 17/693 (2006.01); G06F 30/33 (2020.01); G11C 13/00 (2006.01); H03K 19/17728 (2020.01); H03K 19/1776 (2020.01); G06F 30/331 (2020.01);
U.S. Cl.
CPC ...
H03K 19/17756 (2013.01); G06F 30/33 (2020.01); G11C 13/003 (2013.01); H03K 17/693 (2013.01); H03K 19/177 (2013.01); H03K 19/1776 (2013.01); H03K 19/17728 (2013.01); G06F 30/331 (2020.01);
Abstract

Provided is an integrated circuit that has reduced power consumption. The integrated circuit is provided with: a plurality of first wires one end of each of which is used as an input terminal; a plurality of second wires one end of each of which is used as an output terminal and which are respectively connected to the first wires; a bias wire which is connected to each of the second wires, and which is connected to a power supply or ground; a plurality of switches which connect the first wires or the bias wire and the second wires; and a selection circuit which selects electrical connection between the bias wire and the power supply or ground.


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