The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2020

Filed:

Oct. 06, 2016
Applicant:

Sharp Kabushiki Kaisha, Sakai, Osaka, JP;

Inventors:

Fumiki Nakano, Sakai, JP;

Kiyoshi Minoura, Sakai, JP;

Shigeyasu Mori, Sakai, JP;

Makoto Nakazawa, Sakai, JP;

Takatoshi Orui, Sakai, JP;

Assignee:

SHARP KABUSHIKI KAISHA, Sakai, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01Q 9/04 (2006.01); H01Q 3/26 (2006.01); H01Q 3/44 (2006.01); H01Q 21/00 (2006.01); H01Q 21/06 (2006.01); H01Q 21/24 (2006.01); H01Q 25/00 (2006.01); G02F 1/1368 (2006.01); G02F 1/1362 (2006.01); H01L 29/786 (2006.01); H01Q 19/10 (2006.01); H01Q 21/20 (2006.01);
U.S. Cl.
CPC ...
H01Q 3/2605 (2013.01); G02F 1/1362 (2013.01); G02F 1/1368 (2013.01); H01L 27/124 (2013.01); H01L 27/1222 (2013.01); H01L 27/1225 (2013.01); H01L 27/1255 (2013.01); H01L 29/7869 (2013.01); H01L 29/78669 (2013.01); H01Q 3/44 (2013.01); H01Q 9/0407 (2013.01); H01Q 19/10 (2013.01); H01Q 21/0012 (2013.01); H01Q 21/064 (2013.01); H01Q 21/24 (2013.01); H01Q 25/001 (2013.01); G02F 2203/24 (2013.01); H01Q 21/20 (2013.01);
Abstract

A scanning antenna is a scanning antenna in which antenna units U are arranged, and includes a TFT substrate including a first dielectric substrate, TFTs, a plurality of gate bus lines, source bus lines, and patch electrodes; a slot substrate including a second dielectric substrate, and a slot electrode formed on a first main surface of the second dielectric substrate; a liquid crystal layer LC provided between the TFT substrate and the slot substrate; and a reflective conductive plate provided opposing a second main surface of the second dielectric substrate opposite to the first main surface via a dielectric layer. The slot electrode includes slots arranged in correspondence with the plurality of patch electrodes, and each of the patch electrodes is connected to a drain of a corresponding TFT and is supplied with a data signal from a corresponding source bus line while selected by a scanning signal supplied from the gate bus line of the corresponding TFT. The frequency at which the polarity of the voltage applied to each of the plurality of patch electrodes is inverted is greater than or equal to 300 Hz.


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