The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2020

Filed:

Mar. 20, 2019
Applicant:

Industrial Technology Research Institute, Hsin-Chu, TW;

Inventors:

Jung-Tse Tsai, Hsinchu County, TW;

Po-Chun Yeh, Taichung, TW;

Chien-Hua Hsu, New Taipei, TW;

Po-Tsung Tu, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/338 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7786 (2013.01); H01L 29/122 (2013.01); H01L 29/2003 (2013.01); H01L 29/66431 (2013.01); H01L 29/66462 (2013.01); H01L 29/778 (2013.01); H01L 2924/13064 (2013.01);
Abstract

An enhancement mode GaN transistor is provided, which includes a GaN layer, a quantum well structure, a gate, a source a drain and a first barrier layer. The quantum well structure is disposed on the upper surface of the GaN layer. The gate is disposed on the quantum well structure. The source is disposed on one end of the upper surface of the GaN layer. The drain is disposed on the other end of the upper surface of the GaN layer. The first barrier layer is disposed on the upper surface of the GaN layer and extends to the lateral surfaces of the quantum well structure.


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