The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2020

Filed:

Mar. 09, 2018
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Eng Huat Toh, Singapore, SG;

Shyue Seng Tan, Singapore, SG;

Elgin Kiok Boone Quek, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/112 (2006.01); H01L 27/088 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 27/115 (2017.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/84 (2013.01); H01L 21/845 (2013.01); H01L 27/0886 (2013.01); H01L 27/115 (2013.01); H01L 27/11206 (2013.01); H01L 27/1203 (2013.01); H01L 27/1211 (2013.01); H01L 29/0653 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01);
Abstract

Methods of forming a compact FDSOI OTP/MTP cell and a compact FinFET OTP/MTP cell and the resulting devices are provided. Embodiments include forming a SOI region or a fin over a BOX layer over a substrate; forming a first and a second gate stack, laterally separated, over respective portions of the SOI region or the fin; forming a first and a second liner along each first and second sidewall and of the first and the second gate stack, respectively, the second sidewall over respective portions of the SOI region or the fin; forming a spacer on each first and second liner; forming a S/D region in the SOI region or the fin between the first and the second gate stack; forming a CA over the S/D region; utilizing each gate of the first gate stack and the second gate stack as a WL; and connecting a BL to the CA.


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