The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2020

Filed:

Feb. 15, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Byongju Kim, Hwaseong-si, KR;

Young-min Ko, Hwaseong-si, KR;

Jong-uk Kim, Yongin-si, KR;

Kwangmin Park, Seoul, KR;

Jeong-hee Park, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 45/00 (2006.01); H01F 10/32 (2006.01); H01L 43/02 (2006.01); H01L 43/12 (2006.01); H01L 27/22 (2006.01); H01L 43/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2481 (2013.01); H01L 27/2427 (2013.01); H01L 45/06 (2013.01); H01L 45/08 (2013.01); H01L 45/126 (2013.01); H01L 45/1233 (2013.01); H01L 45/16 (2013.01); H01F 10/329 (2013.01); H01F 10/3254 (2013.01); H01L 27/224 (2013.01); H01L 43/02 (2013.01); H01L 43/10 (2013.01); H01L 43/12 (2013.01); H01L 45/144 (2013.01); H01L 45/146 (2013.01);
Abstract

There is provided a variable resistance memory device including a first electrode line layer including first electrode lines extending in a first direction and spaced apart from each other on a substrate, a second electrode line layer that is above the first electrode line layer and including second electrode lines extending in a second direction orthogonal to the first direction and spaced apart from each other, and a memory cell layer including memory cells between the first electrode line layer and the second electrode line layer. Each of the memory cells includes a selection device layer, an intermediate electrode layer, and a variable resistance layer. A first insulating layer is between the first electrode lines, a second insulating layer is between the memory cells, and a third insulating layer is between the second electrode lines. The second insulating layer includes air gaps on side surfaces of the memory cells.


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