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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10720447 B1

PDFFull Text
Date of Patent:
Jul. 21, 2020

Filed:

Jul. 16, 2019

Integrated circuit memory devices having impurity-doped dielectric regions therein and methods of forming same

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Woo Jin Jang, Suwon-si, KR;

Young Jin Noh, Suwon-si, KR;

Jun Kyu Yang, Seoul, KR;

Bio Kim, Seoul, KR;

Kyong Won An, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., , KR;

Attorney:

Myers Bigel, P.A.

Primary Examiner:

David Vu

Assistant Examiner:

Brandon C Fox

Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/51 (2006.01); H01L 23/528 (2006.01); H01L 21/311 (2006.01); H01L 21/3115 (2006.01); H01L 21/02 (2006.01); H01L 23/522 (2006.01); H01L 21/28 (2006.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0223 (2013.01); H01L 21/3115 (2013.01); H01L 21/31111 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/1157 (2013.01); H01L 29/0649 (2013.01); H01L 29/1037 (2013.01); H01L 29/40117 (2019.08); H01L 29/513 (2013.01); H01L 27/11565 (2013.01); H01L 29/518 (2013.01);
Abstract

An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.

Find Patent Forward Citations

Jang, Woo. (2020). Integrated circuit memory devices having impurity-doped dielectric regions therein and methods of forming same (U.S. Patent No. 10720447). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10720447

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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