The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2020

Filed:

Nov. 02, 2018
Applicant:

Littelfuse, Inc., Chicago, IL (US);

Inventors:

Gi-Young Jeun, Bucheon-si, KR;

Kang Rim Choi, Cupertino, CA (US);

Assignee:

Littelfuse, Inc., Chicago, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/28 (2006.01); H05K 7/00 (2006.01); H01L 23/373 (2006.01); H01L 23/433 (2006.01); H01L 23/495 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3735 (2013.01); H01L 21/56 (2013.01); H01L 23/4334 (2013.01); H01L 23/49562 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48472 (2013.01); H01L 2224/49111 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13034 (2013.01); H01L 2924/181 (2013.01);
Abstract

A packaged power transistor device includes a Direct-Bonded Copper ('DBC') substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.


Find Patent Forward Citations

Jeun, Gi-Young. (2020). Discrete power transistor package having solderless dbc to leadframe attach (U.S. Patent No. 10720376). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10720376

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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