The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2020

Filed:

Jun. 05, 2015
Applicant:

Gsi Technology, Inc., Sunnyvale, CA (US);

Inventors:

Mu-Hsiang Huang, San Jose, CA (US);

Robert Haig, Austin, TX (US);

Patrick Chuang, Cupertino, CA (US);

Lee-Lean Shu, Los Altos, CA (US);

Assignee:

GSI TECHNOLOGY, INC., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 8/12 (2006.01); G11C 11/418 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 8/12 (2013.01); G11C 11/418 (2013.01); G11C 7/1087 (2013.01);
Abstract

Multi-bank, dual-pipe SRAM systems, methods, processes of operating such SRAMs, and/or methods of fabricating multi-bank, dual-pipe SRAM are disclosed. For example, one illustrative multi-bank, dual-pipe SRAM may comprise features for capturing read and write addresses, splitting and/or combining them via one or more splitting/combining processes, and/or bussing them to the SRAM memory banks, where they may be read and written to a particular bank. Illustrative multi-bank, dual-pipe SRAMs and methods herein may also comprise features for capturing two beats of write data, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each SRAM bank, where they may be split/combined/recombined via one or more processes to write data to particular memory bank(s).


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