The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2020

Filed:

Jun. 25, 2019
Applicant:

Socionext Inc., Kanagawa, JP;

Inventor:

Yoshinobu Yamagami, Yokohama, JP;

Assignee:

SOCIONEXT INC., Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 7/12 (2006.01); G11C 8/08 (2006.01); G11C 5/14 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); G11C 5/145 (2013.01); G11C 7/109 (2013.01); G11C 7/1084 (2013.01); G11C 7/1087 (2013.01); G11C 7/1096 (2013.01); G11C 7/222 (2013.01); G11C 8/08 (2013.01);
Abstract

In a semiconductor memory device, a memory cell array includes a plurality of memory cells. A write circuit includes a negative potential generating circuit that generates a potential lower than a lower power supply potential applied to the memory cells. When a write mask signal indicates an enabled state, the write circuit activates the negative potential generating circuit, and supplies the potential generated by the negative potential generating circuit to a bit line to be supplied with low data. On the other hand, when the write mask signal indicates a disabled state, the write circuit supplies no data to bit line pairs, and inactivates the negative potential generating circuit.


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