Technique to lower switching power of bit-lines by adiabatic charging of sram memories

Abstract

A system and method for efficiently managing switching power of bit lines. In various embodiments, a first bit line in a memory array is pre-charged in multiple discrete steps, rather than in one continuous step. For a read operation that completed and read a logic low level from a first storage node, the first bit line is pre-charged from a ground reference level to a first power supply voltage. Similarly, a second bit line corresponding to a second storage node storing an inverse voltage level of the first storage node is pre-charged from a larger second power supply voltage to the smaller first power supply voltage. When the first time interval has elapsed, the first and second bit lines are pre-charged from the first power supply voltage to the second power supply voltage during a second time interval. Discrete steps are also used for pre-charging after write operations.