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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10719294 B1

PDFFull Text
Date of Patent:
Jul. 21, 2020

Filed:

Dec. 18, 2019

Hardware sort accelerator sharing first level processor cache

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Christian Jacobi, West Park, NY (US);

Aditya Puranik, Maharashtra, IN;

Martin Recktenwald, Schoenaich, DE;

Christian Zoellin, Weinstadt, DE;

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorneys:

Cantor Colburn LLP

William Kinnaman

Primary Examiner:

Matthew D Sandifer

Int. Cl.
CPC ...
G06F 7/16 (2006.01); G06F 7/24 (2006.01); G06F 7/08 (2006.01); G06F 7/36 (2006.01); G06F 7/02 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 7/16 (2013.01); G06F 7/02 (2013.01); G06F 7/08 (2013.01); G06F 7/24 (2013.01); G06F 7/36 (2013.01); G06F 9/5027 (2013.01); Y10S 707/99937 (2013.01);
Abstract

A computer processor includes a memory unit that stores key values to be loaded into a partial tournament sort, and a processor cache that obtains tree data from the memory unit indicating the key values. A hardware merge sort accelerator generates a tournament tree based on the key values, and performs a partial tournament sort to store a first portion of tournament results in the processor cache while excluding a second portion of the tournament results from the processor cache.

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