The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2020
Filed:
Oct. 21, 2016
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Uwe Eckhardt, Dresden, DE;
Juergen Boldt, Dresden, DE;
Matthias Baer, Hohenstein-Ernstthal, DE;
Dirk Fimmel, Radebeul, DE;
Karl-Heinz Sandig, Dresden, DE;
Assignee:
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2020.01); H03F 3/45 (2006.01); G11C 29/50 (2006.01); G11C 29/28 (2006.01); G11C 29/48 (2006.01); G11C 29/12 (2006.01); G11C 29/02 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2621 (2013.01); G11C 29/021 (2013.01); G11C 29/022 (2013.01); G11C 29/1201 (2013.01); G11C 29/28 (2013.01); G11C 29/48 (2013.01); G11C 29/50 (2013.01); G11C 2029/5002 (2013.01); G11C 2029/5004 (2013.01);
Abstract
The present disclosure relates to circuit structures and, more particularly, to circuit structures which detect high speed and high precision characterization of VTsat and VTlin of FET arrays and methods of manufacture and use. The circuit includes a control loop comprised of a differential amplifier, a plurality of FET arrays, and at least one analog switch enabling selection between a calibration mode and an operation mode.