The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Aug. 07, 2019
Applicant:

Analog Devices International Unlimited Company, Limerick, IE;

Inventors:

Xudong Wang, Colorado Springs, CO (US);

William B. Beckwith, Larkspur, CO (US);

Michael W. Bagwell, Colorado Springs, CO (US);

Thomas E. Schiltz, Colorado Springs, CO (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 25/03 (2006.01); H03H 7/24 (2006.01); H03H 7/18 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03878 (2013.01); H03H 7/18 (2013.01); H03H 7/24 (2013.01);
Abstract

An electronic circuit can include a gain adjustment circuit (e.g., a gain 'equalizer' circuit), such as to compensate for a variation in insertion loss over a specified range of frequencies. For example, such a gain adjustment circuit can provide an insertion loss characteristic having a specified slope. Such a slope can include a positive slope where insertion loss increases with respect to frequency, or a negative slope where insertion loss decreases with respect to frequency, as illustrative examples. A gain equalization technique can be used to compensate for variation in insertion loss versus frequency between different circuit paths, such as in relation to a switchable delay line having two or more selectable paths, such as for phase shifting applications. A gain adjustment circuit can be configured to provide relatively flat or constant time-domain delay versus frequency, such as inhibiting or reducing dispersion.


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