The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Oct. 14, 2019
Applicant:

Ciena Corporation, Hanover, MD (US);

Inventors:

Mahdi Parvizi, Kanata, CA;

Sadok Aouini, Gatineau, CA;

Naim Ben-Hamida, Nepean, CA;

Assignee:

Ciena Corporation, Hanover, MD (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/093 (2006.01); H03L 7/099 (2006.01); H03L 7/089 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0995 (2013.01); H03L 7/089 (2013.01); H03L 7/093 (2013.01);
Abstract

Described herein is a digital phase locked loop (PLL) which includes a phase frequency detector (PFD) outputting a pulse width modulated (PWM) up pulse and a PWM down pulse based on comparison of a reference clock and a feedback clock, a digital integral circuit connected to the PFD, the digital integral circuit outputting a digital control signal based on the PWM up and down pulses, and a controlled oscillator (CO) connected to the digital integral circuit and an output and input of the PFD. The CO receiving the PWM up and down pulses from the PFD and adjusting a frequency of the CO based on the digital control signal and the PWM up and down pulses to generate an output clock. The feedback clock is based on the output clock and the reference clock is aligned with the feedback clock by adjusting the output clock frequency until frequency/phase lock.


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