The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Apr. 30, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Guolei Yu, Singapore, SG;

Ajay Kumar Kosaraju, Singapore, SG;

Marko Koski, Chandler, AZ (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 5/00 (2006.01); H03K 7/08 (2006.01); H03L 7/081 (2006.01); H03L 7/093 (2006.01);
U.S. Cl.
CPC ...
H03K 5/00 (2013.01); H03K 5/00006 (2013.01); H03K 7/08 (2013.01); H03L 7/0812 (2013.01); H03L 7/093 (2013.01); H03K 2005/00032 (2013.01);
Abstract

An apparatus is disclosed that includes a voltage-controlled delay generator. In an example aspect, the apparatus includes voltage-controlled timing circuitry, duty cycle detection circuitry, and output circuitry. The voltage-controlled timing circuitry is configured to receive a control voltage. The voltage-controlled timing circuitry includes a current source, a control transistor, and a capacitor that are configured to produce a voltage indicator based on the control voltage. The duty cycle detection circuitry is coupled to the voltage-controlled timing circuitry. The duty cycle detection circuitry is configured to detect the voltage indicator and provide a duty cycle indicator based on the voltage indicator. The output circuitry is coupled to the duty cycle detection circuitry and is configured to generate a duty signal based on the duty cycle indicator.


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