The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Jun. 04, 2019
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

Saurabh Singh, Cedar Park, TX (US);

Vamsikrishna Parupalli, Austin, TX (US);

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 4/50 (2006.01); H03H 11/04 (2006.01);
U.S. Cl.
CPC ...
H03K 4/50 (2013.01); H03H 11/04 (2013.01);
Abstract

A system may include a ramp generation circuit for generating a ramp waveform and comprising a first passive circuit element having an impedance pertinent to generation of the ramp waveform and a control circuit comprising a second passive circuit element which is impedance-correlated to the first passive circuit element. The control circuit may be configured to use the second passive circuit element to generate a control signal for controlling the ramp generation circuit, such that a correlation between the first passive circuit element and the second passive circuit element substantially cancels physical variations of the first passive circuit element and the second passive circuit element and use a control signal clock for generating the control signal that is related to a ramp generation clock for generating the ramp waveform such that a magnitude of the ramp waveform remains substantially independent of frequency of operation.


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