Thin-film transistor fabrication method for reducing size of thin-film transistor and pixel area

Abstract

The present invention provides a thin-film transistor and a fabrication method thereof, and an array substrate. The thin-film transistor includes a separation layer () arranged between the source electrode () and the drain electrode (). An oxide semiconductor channel layer () is arranged on one side of the separation layer () and the drain electrode () to contact a portion of an upper surface of the drain electrode (), a side surface of the drain electrode () and the organic separation layer (), and a portion of an upper surface of the source electrode () to serve as a vertical channel, of which a channel length corresponds to a thickness of the separation layer (). Varying the thickness of the separation layer to reduce the length of the vertical channel to a sub-micrometer order would greatly reduce the size of the thin-film transistor and reduce the area of a pixel. The vertical channel does not cause a short channel effect so as to improve electrical performance of the thin-film transistor. Using a multiple-layered hexagonal boron nitride film to make a moisture/oxygen barrier layer () and using a double-layered graphene film to make the source electrode () and the drain electrode () help significantly improve bending durability of the thin-film transistor.