The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Jun. 28, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Brent A. Anderson, Jericho, VT (US);

Edward J. Nowak, Shelburne, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823487 (2013.01); H01L 21/31116 (2013.01); H01L 21/32136 (2013.01); H01L 21/823456 (2013.01); H01L 27/088 (2013.01); H01L 29/42364 (2013.01); H01L 29/4966 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H01L 21/823462 (2013.01);
Abstract

The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the semiconductor substrate. The method further includes prior to depositing a gate on a second vertical FET on the semiconductor substrate, depositing a second layer on the second vertical FET on the semiconductor substrate. The method further includes etching the first layer on the first vertical FET to a lower height than the second layer on the second vertical FET. The method further includes depositing a gate material on both the first vertical FET and the second vertical FET. The method further includes etching the gate material on both the first vertical FET and the second vertical FET to a co-planar height.


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