The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Nov. 25, 2019
Applicant:

Ultramemory Inc., Tokyo, JP;

Inventors:

Yasutoshi Yamada, Tokyo, JP;

Kouji Uemura, Tokyo, JP;

Takao Adachi, Tokyo, JP;

Assignee:

ULTRAMEMORY INC., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 29/04 (2006.01); G11C 11/407 (2006.01); H01L 25/065 (2006.01); H01L 25/07 (2006.01); G11C 5/00 (2006.01); H01L 25/18 (2006.01); G11C 29/00 (2006.01); G11C 29/44 (2006.01); G11C 7/12 (2006.01); G11C 29/12 (2006.01); G11C 8/08 (2006.01);
U.S. Cl.
CPC ...
G11C 5/14 (2013.01); G11C 5/00 (2013.01); G11C 11/407 (2013.01); G11C 29/006 (2013.01); G11C 29/04 (2013.01); G11C 29/4401 (2013.01); G11C 29/781 (2013.01); G11C 29/785 (2013.01); G11C 29/814 (2013.01); H01L 25/065 (2013.01); H01L 25/07 (2013.01); H01L 25/18 (2013.01); G11C 7/12 (2013.01); G11C 8/08 (2013.01); G11C 2029/0403 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01); G11C 2029/1208 (2013.01);
Abstract

The purposes of the present invention are: to provide a layered semiconductor device capable of improving production yield; and to provide a method for producing said layered semiconductor device. This layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. In such a configuration, the semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches. The semiconductor chips and the reserve semiconductor chip are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.


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