The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Aug. 02, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventor:

Seong-hwan Jeon, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); H01L 25/10 (2006.01); G06F 13/16 (2006.01); G06F 3/06 (2006.01); H01L 25/18 (2006.01); G11C 7/22 (2006.01); G11C 5/04 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 5/063 (2013.01); G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 13/1689 (2013.01); G11C 5/04 (2013.01); G11C 7/1093 (2013.01); G11C 7/225 (2013.01); H01L 25/105 (2013.01); H01L 25/18 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01);
Abstract

A semiconductor package with clock sharing, which is suitable for an electronic system having low power consumption characteristics, is provided. The semiconductor package includes a lower package including a lower package substrate and a memory controller mounted on the lower package substrate, an upper package stacked on the lower package and including an upper package substrate and a memory device mounted on the upper package substrate, and a plurality of vertical interconnections electrically connecting the lower package to the upper package. The semiconductor package is configured to cause the memory controller to output a first data clock signal used for a channel that is an independent data interface between the memory controller and the memory device, branch the first data clock signal, and provide the branched first data clock signal to the memory device.


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