The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Nov. 15, 2018
Applicant:

Shanghai Tianma Am-oled Co., Ltd., Shanghai, CN;

Inventors:

Renyuan Zhu, Shanghai, CN;

Yue Li, Shanghai, CN;

Dongxu Xiang, Shanghai, CN;

Yana Gao, Shanghai, CN;

Xingyao Zhou, Shanghai, CN;

Gaojun Huang, Shanghai, CN;

Yilin Xu, Shanghai, CN;

Zhonglan Cai, Shanghai, CN;

Juan Zhu, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 5/10 (2006.01); G09G 3/20 (2006.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
G09G 5/10 (2013.01); G09G 3/20 (2013.01); G11C 19/287 (2013.01); G09G 2310/0243 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01);
Abstract

The present disclosure provides a driving circuit, a method for controlling light emission, and a display device. The driving circuit includes one or more light emission shift registers, each of which includes a first processing module configured to control a signal at a first node based on signals at the input signal terminal, the first clock signal terminal and the second clock signal terminal; a second processing module including first and second transistors, wherein the first transistor is a dual-gate transistor, and the second transistor has a first terminal electrically connected to the pulse signal terminal and a second terminal electrically connected to the second node; and an output module configured to control a signal at an output signal terminal based on the signals at the first level signal terminal, the second level signal terminal, the first node and the second node.


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