The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Apr. 16, 2018
Applicant:

Lapis Semiconductor Co., Ltd., Kanagawa, JP;

Inventors:

Hiroshi Tsuchi, Kanagawa, JP;

Takeshi Nosaka, Kanagawa, JP;

Koji Higuchi, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/2011 (2013.01); G09G 3/3688 (2013.01); G09G 3/3696 (2013.01); G09G 2310/027 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/06 (2013.01); G09G 2320/0276 (2013.01);
Abstract

An output circuit includes a differential amplifier including an inverting input terminal, non-inverting input terminals and an output terminal, and outputs, from the output terminal, a voltage having a level corresponding to a weighted average of respective input voltage levels of the non-inverting input terminals, when the output voltage level is equal to a input voltage level of the inverting input terminal, and outputs a voltage having a level corresponding to a difference between a level corresponding to a weighted average of the respective input voltage levels of the non-inverting input terminals and the input voltage level, when which the output voltage level is different from the input voltage level; and a delay circuit that generates a delay voltage responding with a predetermined time constant with respect to a change in the output voltage level and supplies the delay voltage to the inverting input terminal.


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