The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2020
Filed:
Oct. 03, 2017
Applicant:
Cnex Labs, Inc., San Jose, CA (US);
Inventors:
Xiaojie Zhang, Saratoga, CA (US);
Yi Liu, San Diego, CA (US);
Assignee:
CNEX LABS, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 11/00 (2006.01); G06F 3/06 (2006.01); G11C 16/26 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G06F 11/004 (2013.01); G06F 3/061 (2013.01); G06F 3/0619 (2013.01); G06F 3/0655 (2013.01); G06F 3/0688 (2013.01); G06F 11/008 (2013.01); G11C 11/5642 (2013.01); G11C 16/26 (2013.01);
Abstract
A storage system includes: a control processor, configured to: read user data, generate a bit flip array from the user data including limiting a threshold offset range, and select an optimal read threshold set from the bit flip array; and a non-volatile memory array, coupled to the control processor, configured to store the user data; and wherein the control processor is further configured read a sector N with the optimal read threshold set for enhancing performance of the non-volatile memory array.