The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2020
Filed:
Jan. 31, 2018
Georgia Tech Research Corporation, Atlanta, GA (US);
David Chong Zhang, Atlanta, GA (US);
Arijit Raychowdhury, Atlanta, GA (US);
Madhavan Swaminathan, Marietta, GA (US);
GEORGIA TECH RESEARCH CORPORATION, Atlanta, GA (US);
Abstract
Power supply rejection (PSR) peaking in Low Dropout (LDO) voltage regulators can lead to reduced bandwidth and efficiency. The present invention is directed to a new design method by combining power transmission lines (PTL) with LDOs for enhancing its bandwidth and efficiency. This approach is applicable for LDOs regulating high speed I/O drivers. The PTL combined with decoupling capacitors on the package or board are used to mitigate the PSR peaking. This methodology is demonstrated using printed circuit board test vehicles with off-the-shelf components. When compared to conventional approaches, the PTL solution showed ˜80% lower power supply noise.