The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Nov. 17, 2016
Applicant:

Nederlandse Organisatie Voor Toegepast-natuurwetenschappelijk Onderzoek Tno, s-Gravenhage, NL;

Inventors:

Stefan Kuiper, 's-Gravenhage, NL;

Erwin John van Zwet, 's-Gravenhage, NL;

Stefan Michael Bruno Bäumer, 's-Gravenhage, NL;

Hamed Sadeghian Marnani, 's-Gravenhage, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 7/20 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
G03F 7/70633 (2013.01); G03F 7/70625 (2013.01); G03F 7/70683 (2013.01); H01L 22/12 (2013.01); H01L 22/20 (2013.01);
Abstract

This document describes a method of determining an overlay error during manufacturing of a multilayer semiconductor device. Manufacturing of the semiconductor device comprises forming a stack of material layers comprising depositing of at least two subsequent patterned layers of semiconductor material, the patterned layers comprising a first patterned layer having a first marker element and a second patterned layer having a second marker element. The determining of the overlay error comprises determining relative positions of the first and second marker element in relation to each other, such as to determine the overlay error between the first patterned layer and the second patterned layer. In addition an imaging step is performed on at least one of said first and second patterned layer, for determining relative positions of the respective first or second marker element and a pattern feature of a device pattern comprised by said respective first and second patterned layer.


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