The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

Dec. 01, 2017
Applicant:

Nec Corporation, Minato-ku, Tokyo, JP;

Inventor:

Masaaki Tanio, Tokyo, JP;

Assignee:

NEC CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 3/00 (2006.01); G06F 7/509 (2006.01); G06F 7/544 (2006.01); H03M 1/66 (2006.01); H04L 27/12 (2006.01); H04L 27/36 (2006.01);
U.S. Cl.
CPC ...
H03M 3/322 (2013.01); G06F 7/5095 (2013.01); G06F 7/544 (2013.01); H03M 1/66 (2013.01); H04L 27/12 (2013.01); H04L 27/36 (2013.01);
Abstract

A second-order ΔΣ modulator includes a plurality of integrators and a parallel higher-bit processing part, and the parallel higher-bit processing part includes a plurality of addition and determination processing sections. The addition and determination processing section receives first and second carry inputs and first and second state inputs, and outputs a quantized output and first and second state outputs. A first selector selects one set from sets of the first and the second state outputs from the plurality of addition and determination processing sections and outputs the selected set, and a second selector selects one quantized output from the quantized outputs from the plurality of addition and determination processing sections. An output of the first selector is used as a selection control signal for the first and the second selectors.


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