The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

Jun. 21, 2017
Applicant:

Csmc Technologies Fab2 Co., Ltd., Wuxi New District, Jiangsu, CN;

Inventors:

Xueyan Wang, Jiangsu, CN;

Qiang Chen, Jiangsu, CN;

Assignee:

CSMC TECHNOLOGIES FAB2 CO., LTD., Wuxi New District, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/03 (2006.01); H03K 5/134 (2014.01); H03B 5/20 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0315 (2013.01); H03B 5/20 (2013.01); H03K 3/03 (2013.01); H03K 3/0322 (2013.01); H03K 5/134 (2014.07); H03L 7/0995 (2013.01);
Abstract

A ring voltage control oscillator includes: a conversion unit (), cascaded multistage delay units () and cascaded multistage isolation buffer units (). The conversion unit () receives a voltage signal controlled by the external, converts the voltage signal into a current signal and respectively transmits the current signal to a plurality of delay units () and a plurality of isolation buffer units (). The delay unit () comprises two signal input terminals and two signal output terminals; the isolation buffer unit () comprises two signal input terminals and two signal output terminals; a first signal input terminal and a second signal input terminal of the isolation buffer unit () are correspondingly connected to a first signal output terminal and a second signal output terminal of the same stage of the delay unit (), respectively; clock signals outputted by first signal output terminals of two adjacent stages of the isolation buffering units () have the same phase difference; clock signals outputted by the second signal output terminals of two adjacent stages of the isolation buffering units () have the same phase difference.


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