The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2020
Filed:
Mar. 28, 2018
Applicant:
Alliacense Limited, Llc, Los Altos, CA (US);
Inventor:
Vojin G. Oklobdzija, Berkeley, CA (US);
Assignee:
Other;
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/011 (2006.01); H03L 7/06 (2006.01); H03L 1/02 (2006.01); H03B 5/24 (2006.01);
U.S. Cl.
CPC ...
H03K 3/011 (2013.01); H03B 5/24 (2013.01); H03L 1/02 (2013.01); H03L 7/06 (2013.01);
Abstract
A system of free running oscillators synchronized to the lowest frequency running one and following PVT variation generates a system clock. A method is particularly applicable to clock relatively small clock domains within a multi-core chip containing thousands of cores, and where the clock domain encompasses one or more cores and additional logic blocks. The resulting system clock is divided by 2using latches or flip-flops to achieve a symmetric 50-50 duty cycle of the system clock. Further, such PVT insensitive system clock can be used as a reference for a PLL or DLL generated clock for the domain.