The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

Sep. 26, 2017
Applicant:

Sharp Kabushiki Kaisha, Sakai, Osaka, JP;

Inventors:

Kazuhiro Natsuaki, Sakai, JP;

Takahiro Takimoto, Sakai, JP;

Masayo Uchida, Sakai, JP;

Assignee:

SHARP KABUSHIKI KAISHA, Sakai, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/107 (2006.01); H01L 29/06 (2006.01); H01L 31/02 (2006.01); H01L 31/0203 (2014.01); H01L 31/0236 (2006.01);
U.S. Cl.
CPC ...
H01L 31/107 (2013.01); H01L 29/0642 (2013.01); H01L 31/0203 (2013.01); H01L 31/02027 (2013.01); H01L 31/02363 (2013.01);
Abstract

An avalanche photodiode according to the present invention includes, inside a substrate semiconductor layer having a first conductivity type and a uniform impurity concentration, a first semiconductor layer having the first conductivity type, a second semiconductor layer having a second conductivity type, a third semiconductor layer having the second conductivity type, a fourth semiconductor layer having the second conductivity type, a fifth semiconductor layer having the first conductivity type and formed at a position away from the third semiconductor layer in a lateral direction, a sixth semiconductor layer having the second conductivity type, a first contact, and a second contact. The first semiconductor layer is positioned just under the second semiconductor layer and the fifth semiconductor layer in contact therewith. An avalanche phenomenon is caused at a junction between the first semiconductor layer and the second semiconductor layer.


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