The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2020
Filed:
Dec. 24, 2018
Applicants:
Guobiao Zhang, Corvallis, OR (US);
Peter Y. Yu, Oakland, CA (US);
Inventors:
Guobiao Zhang, Corvallis, OR (US);
Peter Y. Yu, Oakland, CA (US);
Assignees:
HangZhou HaiCun Information Technology Co., Ltd., HangZhou, ZheJiang, CN;
Other;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/20 (2006.01); H01L 23/00 (2006.01); H01L 27/088 (2006.01); H01L 27/06 (2006.01); H01L 21/8252 (2006.01); H01L 21/66 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/2003 (2013.01); H01L 21/8252 (2013.01); H01L 22/22 (2013.01); H01L 24/49 (2013.01); H01L 27/0605 (2013.01); H01L 27/088 (2013.01); H01L 29/0696 (2013.01);
Abstract
A GaN-on-Si output transistor array comprises a plurality of small monolithic output transistors. The substrate surface has multiple grids, upon which multiple pieces of the small monolithic GaN films are grown epitaxially on the silicon substrate. Each small monolithic output transistor is formed in a respective small monolithic GaN film. By disabling defective transistors, the overall yield/reliability is improved.