The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

Nov. 16, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kyeong Jin Park, Yongin-si, KR;

Seo-Goo Kang, Seoul, KR;

Kwonsoon Jo, Suwon-si, KR;

Kohji Kanamori, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11573 (2017.01); H01L 23/48 (2006.01); H01L 27/11568 (2017.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 23/481 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 29/1037 (2013.01);
Abstract

Disclosed is a semiconductor memory device comprising a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, a stack structure on the second substrate and comprising a plurality of gate electrodes, a through dielectric pattern penetrating the stack structure and the second substrate, and a vertical supporter on a top surface of the second substrate and vertically extending from the top surface of the second substrate and penetrating the stack structure and the through dielectric pattern.


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