The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

Jun. 29, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sungmi Yoon, Seoul, KR;

Chunhyung Chung, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 27/108 (2006.01); H01L 21/762 (2006.01); H01L 21/3205 (2006.01); H01L 21/321 (2006.01); C23C 16/24 (2006.01); H01L 29/06 (2006.01); C23C 16/44 (2006.01); C23C 16/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10876 (2013.01); C23C 16/0209 (2013.01); C23C 16/24 (2013.01); C23C 16/44 (2013.01); H01L 21/32055 (2013.01); H01L 21/32105 (2013.01); H01L 21/76235 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 29/0649 (2013.01);
Abstract

Provided is a method for manufacturing a semiconductor device including: patterning a substrate to form a plurality of active patterns including two adjacent active patterns having a first trench therebetween; forming a semiconductor layer on the plurality of active patterns to cover the plurality of active patterns; forming a device isolation layer on the semiconductor layer to cover the semiconductor layer for oxidization and fill the first trench; patterning the device isolation layer and the plurality of active patterns so that a second trench intersecting the first trench is formed and the two active patterns protrudes from the device isolation layer in the second trench; and forming a gate electrode in the second trench. Here, a first thickness of the semiconductor layer covering a top surface of each of the two active patterns is greater than a second thickness of the semiconductor layer covering a bottom of the first trench.


Find Patent Forward Citations

Loading…